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VLSI CAD Part II: Layout
Learn key VLSI CAD tools for ASIC/SoC design. Focus on logic-to-layout mapping, placement, routing, and timing analysis.
Course Cost
₹ 2,699
Intermediate
Skill Level
22 Hours
Self-paced lessons
This course, VLSI CAD Part II: Layout, is an in-depth exploration of the computer-aided design (CAD) tools used in creating Application Specific Integrated Circuits (ASIC) and System on Chip (SoC) designs. It focuses on the crucial steps of transforming logic designs into physical layouts. Students will learn about technology mapping, ASIC placement and routing, and timing analysis. The course covers fundamental algorithms and data structures used in these tools, aiming to provide a deep understanding of how they function. Key topics include iterative and analytical placement methods, maze routing techniques, and static timing analysis. This course builds on VLSI CAD Part I: Logic and prepares students to understand and work with advanced VLSI design tools and methodologies.
22,747 Enrolled
English
What you'll learn
Understand the ASIC layout process and the role of technology libraries
Master technology mapping techniques for translating logical designs into real gates
Learn both iterative and analytical placement algorithms for efficient gate positioning
Explore maze routing techniques for connecting placed components
Understand static timing analysis for evaluating design performance
Gain practical experience through programming assignments in placement and routing
Develop skills in analyzing and optimizing VLSI designs using industry-standard CAD techniques
Skills you'll gain
This course includes:
580 Minutes PreRecorded video
7 quizzes, 2 programming assignments
Access on Mobile, Tablet, Desktop
FullTime access
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There are 6 modules in this course
This course dives deep into the VLSI CAD tools essential for ASIC and SoC design, focusing on the critical steps from logic to layout. Students will explore technology mapping, which translates synthesis output into real logic gates. The course covers both iterative and analytical placement algorithms, teaching students how to efficiently position millions of gates on a chip. Routing techniques, particularly maze routing, are examined in detail, showing how to connect the placed components. The course concludes with an in-depth look at static timing analysis, enabling students to evaluate the speed and performance of their designs. Throughout, the emphasis is on understanding the fundamental algorithms and data structures that power these sophisticated CAD tools.
Orientation
Module 1 · 1 Hours to complete
ASIC Placement
Module 2 · 3 Hours to complete
Technology Mapping
Module 3 · 6 Hours to complete
ASIC Routing
Module 4 · 3 Hours to complete
Timing Analysis
Module 5 · 6 Hours to complete
Final Exam
Module 6 · 3 Hours to complete
Fee Structure
Payment options
Financial Aid
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Faculties
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Frequently asked Questions
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