RISC-V Computer Architecture Fundamentals
Master RISC-V architecture using industrial cores and FPGA implementation. Learn practical system-on-chip design and simulation techniques.
Master RISC-V architecture using industrial cores and FPGA implementation. Learn practical system-on-chip design and simulation techniques.
This comprehensive course explores RISC-V computer architecture through hands-on experience with an industrial system-on-chip (SoC) implementation. Students will learn to develop and compile C and RISC-V Assembly code, understand I/O systems, and configure microarchitecture features. The course covers both software simulation and optional hardware implementation using FPGA boards. Through practical exercises and industry-standard benchmarks, students gain expertise in processor design, performance optimization, and hardware-software co-design. The curriculum emphasizes real-world applications using various simulation tools and development environments.
Instructors:
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What you'll learn
Master RISC-V computer architecture principles and implementation
Develop programs using C and RISC-V Assembly language
Understand and configure SoC I/O systems and peripherals
Optimize processor performance using industry-standard benchmarks
Gain practical experience with hardware simulation tools
Skills you'll gain
This course includes:
PreRecorded video
Graded assignments, exams
Access on Mobile, Tablet, Desktop
Limited Access access
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There are 10 modules in this course
This course provides a practical introduction to RISC-V computer architecture using an industrial-grade system-on-chip implementation. Students learn through a combination of theoretical concepts and hands-on programming exercises. The curriculum covers essential topics including C and Assembly programming, peripheral interfaces, interrupt handling, and microarchitecture configuration. Emphasis is placed on practical skills using industry-standard tools and simulation environments.
Installation and Initial Demonstrations
Module 1
C Programming with the RVfpga SoC
Module 2
RISC-V Assembly Programming with the RVfpga SoC
Module 3
RISC-V Function Calls
Module 4
Mixing C and Assembly Functions in a Program
Module 5
Introduction to Peripherals and Input/Output
Module 6
More I/O: 7-Segment Displays
Module 7
More I/O: Timers
Module 8
Interrupts
Module 9
Delving Deeper into the RISC-V VeeR Core
Module 10
Fee Structure
Instructors
1 Course
Distinguished Computer Engineering Professor and Textbook Author
Sarah L. Harris serves as a Professor of Electrical and Computer Engineering at the University of Nevada, Las Vegas, bringing extensive expertise in computer architecture, embedded systems, and digital design. Her impressive career includes positions at prestigious institutions and companies, including Hewlett Packard, Nvidia, and the Technical University of Darmstadt, as well as collaborations with Intel and Imagination Technologies. Before joining UNLV in 2014, she spent a decade as faculty at Harvey Mudd College after earning her M.S. and Ph.D. from Stanford University. Her significant contributions to engineering education include co-authoring three widely-adopted textbooks, most notably "Digital Design and Computer Architecture: RISC-V Edition" (2021), which has been translated into multiple languages and is used by universities worldwide. Currently leading three NSF-funded projects, her research focuses on computer architecture, embedded systems applications, and the intersection of machine learning with biomedical engineering and robotics. Her work has garnered over 1,800 citations, establishing her as a leading voice in computer engineering education and research
1 Course
Computer Architecture Expert and RISC-V Education Pioneer
Daniel A. Chaver-Martinez serves as an Associate Professor at the University Complutense of Madrid (UCM), bringing extensive expertise in computer architecture and processor design. His academic foundation includes a Physics Degree from the University of Santiago de Compostela (1998) and an Electronic Engineering Degree from UCM (2000), followed by a Ph.D. from UCM completed in 2006. His significant contributions to the field include co-authoring the comprehensive RVfpga course with Dr. Sarah Harris, which has been downloaded by more than 2,800 users since its release in 2020. Since 2015, he has maintained a productive collaboration with Imagination Technologies, contributing to processor development and creating educational materials for their University Programme. His research portfolio includes more than 30 published papers and patents in computer architecture, with particular focus on RISC-V architecture and processor design. As an educator, he has developed and taught numerous courses in computer architecture and digital systems, while also contributing to international workshops and educational initiatives that bridge academic theory with practical industry applications
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Frequently asked questions
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