RISC-V Compiler Optimization
Master RISC-V compiler toolchains and optimization techniques. Learn to build, debug, and enhance RISC-V applications using LLVM and GCC.
Master RISC-V compiler toolchains and optimization techniques. Learn to build, debug, and enhance RISC-V applications using LLVM and GCC.
This comprehensive course explores compiler toolchain internals and optimization techniques for RISC-V applications. Designed for engineers and developers, it covers cross-compilation concepts, popular compiler toolchains (LLVM and GCC), debugging techniques, and application optimization. Participants learn to build RISC-V applications, optimize for code size and performance, and understand application demands through instrumentation. The course prepares engineers for roles in toolchain development, systems performance, and RISC-V-based device development, addressing the growing demand for compiler expertise in the RISC-V ecosystem.
Instructors:
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What you'll learn
Master compiler toolchain concepts and cross-compilation techniques
Build RISC-V applications using LLVM and GCC toolchains
Develop expertise in debugging toolchain issues
Implement optimization strategies for code size and performance
Apply instrumentation techniques for application analysis
Skills you'll gain
This course includes:
PreRecorded video
Graded assignments, exams
Access on Mobile, Tablet, Desktop
Limited Access access
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There are 5 modules in this course
This course provides a comprehensive introduction to RISC-V compiler toolchains and optimization techniques. Participants learn about compiler internals, cross-compilation concepts, and practical application building using both LLVM and GCC toolchains. The curriculum covers debugging methodologies, performance optimization strategies, and instrumentation techniques for understanding application demands. Special emphasis is placed on practical skills needed for toolchain development and systems performance engineering.
Compiler Toolchains
Module 1
Introduction to Compiler Optimizations
Module 2
Building RISC-V Applications
Module 3
Debug Toolchain Issues
Module 4
Final Exam
Module 5
Fee Structure
Instructor
1 Course
Distinguished Compiler Engineer and Performance Optimization Expert
Aditya Kumar serves as a Senior Software Engineer at Snap Inc., where he continues his pioneering work in compiler optimization and performance engineering. After completing his master's from Texas A&M University with groundbreaking work on C++ program rejuvenation through demacrofication, he has built an extraordinary career spanning roles at Facebook, Samsung Austin R&D Center, and Qualcomm Innovation Center. His technical impact is most evident through his contributions to LLVM, including the widely-adopted Hot Cold Splitting optimization used in iOS applications and the GVNHoist implementation utilized by major hardware vendors for SPEC benchmarks. As an ACM Distinguished Speaker and program chair of the LLVM workshop at CGO, he regularly shares insights at prestigious conferences including CppCon, RISC-V Global Forum, and Embedded Linux Conference. His expertise spans compiler toolchains, algorithmic optimizations, and performance analysis, with significant contributions to various components including the Clang static analyzer, C++ standard libraries, and GCC's graphite framework. Through his role at Snap, he continues to advance compiler technology while focusing on application performance optimization and startup time improvements for mobile platforms.
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