FPGA Computing Systems: Partial Dynamic Reconfiguration
Learn advanced FPGA partial dynamic reconfiguration techniques for flexible, high-performance computing systems. Master design flows and tools.
Learn advanced FPGA partial dynamic reconfiguration techniques for flexible, high-performance computing systems. Master design flows and tools.
This course delves into the advanced concept of Partial Dynamic Reconfiguration (PDR) in FPGA computing systems. Students will explore reconfigurable hardware contexts, techniques to manage reconfiguration overhead, and compare different design flows for reconfigurable systems. The curriculum covers the evolution of FPGA technologies, from standalone solutions to cloud infrastructures, and discusses future research directions in reconfigurable computing. Through comprehensive modules, learners will understand the principles of dynamic reconfiguration, design methodologies for reconfigurable systems, and the latest trends in FPGA-based cloud computing. The course emphasizes practical applications and challenges in implementing PDR, preparing students for cutting-edge work in adaptive and high-performance computing systems.
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English
Português (Portugal), Русский, Français, 1 more
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What you'll learn
Understand the concept of reconfigurability in FPGAs and its applications
Analyze techniques for managing reconfiguration overhead in dynamic systems
Compare different design flows for realizing reconfigurable FPGA-based systems
Explain the phases of a design flow for FPGA-based system development
Evaluate the benefits and challenges of reconfigurable cloud computing solutions
Understand the evolution of CAD frameworks for FPGA design
Skills you'll gain
This course includes:
27 Hours PreRecorded video
8 assignments
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FullTime access
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There are 4 modules in this course
This course provides an in-depth exploration of Partial Dynamic Reconfiguration (PDR) in FPGA computing systems. It covers the fundamentals of reconfigurable hardware, techniques for managing reconfiguration overhead, and various design flows for implementing reconfigurable systems. The curriculum is structured to guide students from basic concepts to advanced applications, including the use of FPGAs in cloud infrastructures. Key topics include the classification of SoC and SoMC reconfigurations, design methodologies for PDR, CAD tools for reconfigurable system design, and the evolution of FPGA technologies. The course also addresses emerging trends and future research directions in reconfigurable computing, preparing students for the cutting edge of FPGA-based system design.
An Introduction to Reconfigurations
Module 1 · 5 Hours to complete
Towards Partial Dynamic Reconfiguration and Complex FPGA-based systems
Module 2 · 6 Hours to complete
Design Flows
Module 3 · 9 Hours to complete
Closing remarks and future directions
Module 4 · 6 Hours to complete
Fee Structure
Payment options
Financial Aid
Instructor
Leader in Computing Systems and Reconfigurability
Marco Domenico Santambrogio is an Assistant Professor at Politecnico di Milano and a Research Affiliate at the CSAIL lab at MIT. He earned his laurea (M.Sc. equivalent) degree in Computer Engineering from Politecnico di Milano in 2004, followed by a second M.Sc. in Computer Science from the University of Illinois at Chicago (UIC) in 2005, and a Ph.D. in Computer Engineering from Politecnico di Milano in 2008. Dr. Santambrogio was a postdoctoral fellow at CSAIL, MIT, and has held visiting positions at Northwestern University and the Heinz Nixdorf Institute. He is a senior member of both IEEE and ACM, as well as a member of the IEEE Computer Society and the IEEE Circuits and Systems Society. Santambrogio has participated in various program committees for electronic design automation conferences, including DAC, DATE, and FPL. He has been affiliated with the Micro Architectures Laboratory at Politecnico di Milano since its inception, where he established the Dynamic Reconfigurability in Embedded System Design (DRESD) project in 2004. In 2011, he founded the Novel, Emerging Computing System Technologies Laboratory (NECSTLab), combining the MicroLab and VPLab, and continues to lead this innovative research facility.
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